Composite electronic device and digital transmission circuit using thereof

ABSTRACT

A composite electronic device includes first and second magnetic substrates, and a functional layer sandwiched between these magnetic substrates, and the functional layer is configured by a common-mode filter layer and a ESD protection element layer. An electrostatic capacitance of the ESD protection elements is equal to or lower than 0.35 pF. The common-mode filter layer includes a first spiral conductor formed on an insulation layer, and a second spiral conductor formed on an insulation layer. DC resistance of a common mode filter is equal to or higher than 0.5Ω and equal to or lower than 5Ω, and an electrostatic capacitance of the ESD protection elements is equal to or lower than 0.35 pF. A width W and a length L of the first and second spiral conductors satisfy a relational equation expressed by √(L/W)&lt;(7.6651−fc)/0.1385.

TECHNICAL FIELD

The present invention relates to a composite electronic device, and more particularly relates to a composite electronic device configured by combining electrostatic discharge (ESD) protection elements. The present invention also relates to a digital transmission circuit, and more particularly relates to a digital transmission circuit configured by using ESD protection elements and a common-mode filter.

BACKGROUND OF THE INVENTION

In recent years, standards of USB 2.0 and a high-definition multimedia interface (HDMI) have been widely distributed as high-speed signal transmission interfaces, and they are used in many digital devices such as personal computers and digital high-vision televisions. These interfaces employ a differential signal system that transmits a differential signal (a differential mode signal) by using a pair of signal lines, unlike a single-end transmission system that has been generally used for many years.

The differential transmission system has excellent characteristics in that the system is not easily affected by exogenous noise as well as that the system has a small radiation electromagnetic field generated from the signal lines, as compared with the single-end transmission system. Therefore, a signal can have small amplitude, and the system can perform a higher-speed signal transmission than the single-end transmission system, by shortening arise time and a fall time based on the small amplitude.

FIG. 11 is a circuit diagram of a general differential transmission circuit.

The differential transmission circuit shown in FIG. 11 includes a pair of signal lines 1 and 2, an output buffer 3 that supplies a differential mode signal to the signal lines 1 and 2, and an input buffer 4 that receives a differential mode signal from the signal lines 1 and 2. In this configuration, an input signal IN given to the output buffer 3 is transmitted to the input buffer 4 via the pair of signal lines 1 and 2, and is reproduced as an output signal OUT. This differential transmission circuit has a characteristic that a radiation electromagnetic field generated from the signal lines 1 and 2 is small, as described above. However, this circuit generates a relatively large radiation electromagnetic field when common noise (common mode noise) is superimposed on the signal lines 1 and 2. To decrease the radiation electromagnetic field generated by the common mode noise, it is effective to insert a common-mode choke coil 5 into the signal lines 1 and 2, as shown in FIG. 11.

The common-mode choke coil 5 has characteristics that impedance to a differential component (a differential mode signal) transmitted through the signal lines 1 and 2 is low and that impedance to an in-phase component (common mode noise) is high. Therefore, by inserting the common-mode choke coil 5 into the signal lines 1 and 2, common mode noise transmitted through the pair of signal lines 1 and 2 can be interrupted without substantially attenuating the differential mode signal.

In a latest high-speed digital interface such as an HDMI, an IC very sensitive to static electricity is used because the interface handles a fine signal of a high transmission rate. Accordingly, ESD (electrostatic discharge) becomes a large problem. To prevent destruction of the IC due to ESD, a varistor is used as an ESD countermeasure device between the signal lines and a base. However, when the varistor is used, a signal waveform becomes inert, and signal quality is degraded. Therefore, a lower-capacitance ESD countermeasure device is required. For example, as shown in FIG. 12, Japanese Patent Application Laid-open No. 2008-28214 proposes an ESD protection circuit having an electrostatic capacitance of an ESD protection device 9 set to 0.3 pF or lower, by connecting a coil 8 in series on signal lines 7 connected to an IC 6 and by connecting the ESD protection device 9 between each signal line 7 and the ground (see FIG. 8 of Japanese Patent Application Laid-open No. 2008-28214).

Japanese Patent Application Laid-open No. 2007-214166 discloses a structure having a voltage-dependency resistance material having an ESD protection function provided on an uppermost part of a composite electronic device accommodating a common-mode noise filter and the ESD protection function in one package. According to this structure, the voltage-dependency resistance material can be provided after sintering a laminated body containing many insulation layers. With this arrangement, it is possible to prevent reduction of the ESD protection function due to oxidation and cracking of the voltage-dependency resistance material at a sintering time. Consequently, the ESD protection function can be improved.

Furthermore, Japanese Patent Application Laid-open No. 2006-261585 discloses a common mode filter including first and second coil conductors electromagnetically coupled to each other, and having a satisfactory high-frequency characteristic by arranging that a relation between a cutoff frequency fc of the common mode filter and a conductor width W and a total length L of the first coil conductor satisfy relational equation expressed by √(L/W)<(7.6651−fc)/0.1385.

In a conventional circuit configuration shown in FIG. 12, it is preferable that the protection voltage of the IC 6 is as high as possible. The protection voltage in this case means a voltage at which the IC 6 is broken. For example, it is known that a conventional circuit configured by combining a general varistor of 6 pF as a ESD protection element and a common mode filter can secure a protection voltage of 5 kV. However, as described above, because the varistor has a large electrostatic capacitance and its signal quality is degraded, a circuit capable of obtaining a protection voltage equal to or higher than that of a varistor while minimizing the electrostatic capacitance has been desired.

In the common mode filter described in Japanese Patent Application Laid-open No. 2007-214166, the voltage-dependency resistance material constituting ESD protection elements contains a resin. Therefore, the ESD protection elements need to be provided on the uppermost part due to a constraint of a manufacturing step which becomes a large constraint on design. The voltage-dependency resistance material is filled into a very fine gap of about 10 μm. At the uppermost part, an uneven area is large in a plane surface due to a structure that many insulation layers formed with conductor patterns are laminated. Consequently, it is considerably difficult to stably form a very fine gap. Further, in forming the ESD protection elements on a top layer, the manufacturing step becomes complex, and manufacturing cost increases.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a composite electronic device configured by combining ESD protection elements having a smaller electrostatic capacitance than that of a varistor and an excellent discharge characteristic and a common mode filter, and capable of obtaining a protection voltage equal to or higher than 5 kV.

Another object of the present invention is to provide a high-speed digital transmission circuit configured by combining ESD protection elements having a smaller electrostatic capacitance than that of a varistor, an excellent discharge characteristic, and enhanced heat resistance and weatherability and a common mode filter, and capable of obtaining a protection voltage equal to or higher than 5 kV.

As a result of intensive studies to achieve the above objects, the inventor(s) of the present invention has found that a protection voltage equal to or higher than 5 kV can be obtained by setting DC resistance of a common mode filter to equal to or higher than 0.5Ω in a composite electronic device obtained by combining common-mode filter elements and ESD protection elements.

The present invention has been achieved based on the technical findings described above. A composite electronic device according to the present invention includes ESD protection elements absorbing overvoltage caused by electrostatic discharge and a common-mode filter element connected to the ESD protection elements. An electrostatic capacitance of each of the ESD protection elements is equal to or lower than 0.35 pF, and DC resistance of the common-mode filter element is equal to or higher than 0.5Ω.

According to the present invention, a protection voltage equal to or higher than 5 kV can be secured for an IC connected to a latter stage of a composite electronic device. Further, the present invention can provide an ESD protection function having a smaller electrostatic capacitance than that of a varistor and having an excellent discharge characteristic.

In the present invention, common-mode filter element includes first and second spiral conductors that are magnetically coupled to each other and arranged in superimposition in a laminating direction. The thickness of each of the first and second spiral conductors is equal to or smaller than 10 μm. It is preferable that a width W and a length L of the first and second spiral conductors satisfy a relational equation expressed by √(L/W)<(7.6651−fc)/0.1385, when a cutoff frequency of differential mode noise is fc (MHz).

As far as a common mode filter according to the present invention satisfies the relational equation mentioned above, a protection voltage equal to or higher than 5 kV can be secured while maintaining a normal operation of the common mode filter in a high-frequency band of a 800 MHz band.

In the present invention, common-mode filter elements and ESD protection elements are provided between two magnetic substrates. The ESD protection elements include a base insulation layer, electrodes mutually oppositely arranged via gaps on the base insulation layer, and a static-electricity absorbing layer arranged at least between the electrodes. The static-electricity absorbing layer is a composite having a conductive inorganic material discontinuously dispersed in a matrix of an insulation inorganic material.

According to this configuration, the composite electronic device includes low-voltage discharge-type ESD protection elements having a very small electrostatic capacitance, a low discharge starting voltage, and excellent discharge resistance. Therefore, the composite electronic device can transmit a signal equivalent to a signal having no ESD protection, and can suppress reduction of characteristic impedance. Furthermore, because a composite of an insulation inorganic material and a conductive inorganic material is configured as a static-electricity protection material, pressure resistance can be remarkably increased, and weatherability in external environments such as temperature and humidity can be remarkably increased. Further, because inductor elements and ESD protection elements are formed in one chip, a very compact and high-performance electronic device can be provided.

In the present specification, “composite” means a state that a conductive inorganic material is dispersed in a matrix of an insulation inorganic material. This is a concept including not only a state that a conductive inorganic material is dispersed uniformly or at random in a matrix of an insulation inorganic material but also a state that an aggregate of a conductive inorganic material is dispersed in a matrix of an insulation inorganic material, that is, a state generally called a sea-island structure. In the present specification, “insulation” means resistance that is equal to or higher than 0.1 Ωcm, and “conductivity” means resistance that is lower than 0.1 Ωcm. So-called “semiconductivity” is included in the former so long as specific resistance thereof is equal to or higher than 0.1 Ωcm.

In the present invention, a insulation inorganic material is preferably at least one kind selected from a group of Al₂O₃, TiO₂, SiO₂, ZnO, In₂O₃, NiO, CoO, SnO₂, V₂O₅, CuO, MgO, ZrO₂, AlN, BN, and SiC. Because these metal oxides are excellent in insulation, heat resistance, and weatherability, these metal oxides function effectively as materials constituting an insulation matrix of a composite. As a result, it is possible to realize highly-functional ESD protection elements having excellent discharge characteristic, heat resistance, and weatherability. Because these metal oxides are obtainable at a low cost and because a sputtering method can be applied to these metal oxides, productivity and economics can be increased.

In the present invention, a conductive inorganic material is preferably at least one kind of metal or a metal compound of these metals selected from a group of C, Ni, Cu, Au, Ti, Cr, Ag, Pd, and Pt. By compounding these metals or a metal compound in a state of a discontinuous dispersion in a matrix of an insulation inorganic material, highly-functional ESD protection elements having excellent discharge characteristic, heat resistance, and weatherability can be realized.

It is preferable that the first and second spiral conductors have a curved line shape. When the first and second spiral conductors have a circular spiral shape, a total length of these conductors can be set shorter than that of the conductors having a rectangular spiral shape. With this arrangement, a cutoff frequency of differential mode noise of the common mode filter can be set higher, thereby achieving a composite electronic device having higher performance.

The above objects of the present invention can be also achieved by a digital transmission circuit including a pair of signal lines, a semiconductor IC chip connected to the pair of signal lines, ESD protection elements provided at a pre-stage of the semiconductor IC chip on the pair of signal lines, and a common mode filter provided between the ESD protection elements and the semiconductor IC chip on the pair of signal lines, where an electrostatic capacitance of each of the ESD protection elements is equal to or lower than 0.35 pF, and DC resistance of the common mode filter is equal to or higher than 0.5Ω.

According to the present invention, a protection voltage equal to or higher than 5 kV can be secured for the semiconductor IC chip. The present invention can also provide a high-speed digital transmission circuit having an ESD protection function with a smaller electrostatic capacitance than that of a varistor and with an excellent discharge characteristic. Further, because the ESD protection elements are arranged at the pre-stage of the common mode filter, an overvoltage due to static electricity can be reflected at an input end of the common mode filter. The ESD protection elements can absorb at once the overvoltage generated due to an increased voltage as a result of superimposition of a reflection signal. Therefore, absorption efficiency of an overvoltage by the ESD protection elements can be increased.

The present invention can provide a composite electronic device configured by combining ESD protection elements having a small electrostatic capacitance, an excellent discharge characteristic, and excellent heat resistance and weatherability and a common mode filter, and capable of obtaining a protection voltage equal to or higher than 5 kV.

The present invention can also provide a high-speed digital transmission circuit configured by ESD protection elements having a small electrostatic capacitance and an excellent discharge characteristic and a common mode filter, and capable of obtaining a protection voltage equal to or higher than 5 kV.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of this invention will become more apparent by reference to the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic perspective view showing an external configuration of a composite electronic device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a configuration of the composite electronic device 100;

FIG. 3 is a schematic exploded perspective view showing one example of a layer structure of the composite electronic device 100;

FIG. 4 is a schematic plan view showing a positional relationship between the gap electrodes 28 and 29 and other conductor patterns;

FIG. 5A is a schematic plan view showing one example of a layer structure near the first gap electrode 28 in the ESD protection layer 12 b;

FIG. 5B is a schematic cross-sectional view showing one example of a layer structure near the first gap electrode 28 in the ESD protection layer 12 b;

FIG. 6 is a schematic view for explaining a principle of the ESD protection elements;

FIG. 7 is a flowchart showing a manufacturing step of the composite electronic device;

FIG. 8 is a schematic exploded perspective view showing a configuration of a composite electronic device according to a second embodiment of the present invention;

FIG. 9A is a schematic block diagram showing a configuration of a high-speed digital transmission circuit according to a preferred embodiment of the present invention;

FIG. 9B is a schematic block diagrams showing another configuration of a high-speed digital transmission circuit according to a preferred embodiment of the present invention;

FIG. 10 is a graph showing a protection voltage of each of the above examples and corresponding comparative examples;

FIG. 11 is a circuit diagram of a general differential transmission circuit; and

FIG. 12 is a circuit diagram showing a conventional ESD countermeasure circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings.

FIG. 1 is a schematic perspective view showing an external configuration of a composite electronic device according to a first embodiment of the present invention.

As shown in FIG. 1, a composite electronic device 100 according to this embodiment is a thin-film common mode filter having an ESD protection function, and includes first and second magnetic substrates 11 a and 11 b, and a function layer 12 sandwiched between the first magnetic substrate 11 a and the second magnetic substrate 11 b. First to sixth terminal electrodes 13 a to 13 f are formed on an external peripheral circuit of a laminated body constituted by the first magnetic substrate 11 a, the function layer 12, and the second magnetic substrate 11 b. The first and second terminal electrodes 13 a and 13 b are formed on a first side surface 10 a. The third and fourth terminal electrodes 13 c and 13 d are formed on a second side surface 10 b opposite to the first side surface 10 a. The fifth terminal electrode 13 e is formed on a third side surface 10 c orthogonal with the first and second side surfaces 10 a and 10 b. The sixth terminal electrode 13 f is formed on a fourth side surface 10 d opposite to the third side surface.

The first and second magnetic substrates 11 a and 11 b physically protect the function layer 12, and serve as a closed magnetic path of the common mode filter. Sintered ferrite, composite ferrite (a resin containing powdery ferrite), and the like can be used as materials of the first and second magnetic substrates 11 a and 11 b. The first and second magnetic substrates 11 a and 11 b of the present embodiment may have a single layer structure or a multilayer structure.

FIG. 2 is a circuit diagram showing a configuration of the composite electronic device 100.

As shown in FIG. 2, the composite electronic device 100 includes inductor elements 14 a and 14 b functioning as a common-mode choke coil, and ESD protection elements 15 a and 15 b. One ends of the inductor elements 14 a and 14 b are connected to the first and second terminal electrodes 13 a and 13 b, respectively, and the other ends of the inductor elements 14 a and 14 b are connected to the third and fourth terminal electrodes 13 c and 13 d, respectively. One ends of the ESD protection elements 15 a and 15 b are connected to the first and second terminal electrodes 13 a and 13 b, respectively, and the other ends of the ESD protection elements 15 a and 15 b are connected to the fifth and sixth terminal electrodes 13 e and 13 f, respectively. As shown in FIG. 13, the composite electronic device 100 is mounted on a pair of signal lines. In this case, the first and second terminal electrodes 13 a and 13 b are connected to the input side of the signal lines, and the third and fourth terminal electrodes 13 c and 13 d are connected to an output side of the signal lines. The fifth and sixth terminal electrodes 13 e and 13 f are connected to a base line.

FIG. 3 is a schematic exploded perspective view showing one example of a layer structure of the composite electronic device 100.

As shown in FIG. 3, the composite electronic device 100 includes the first and second magnetic substrates 11 a and 11 b, and the function layer 12 sandwiched between the first and second magnetic substrates 11 a and 11 b. The function layer 12 is constituted by a common-mode filter layer 12 a and an ESD protection layer 12 b.

The common-mode filter layer 12 a includes insulation layers 16 a to 16 e, a magnetic layer 16 f, an adhesive layer 16 g, a first spiral conductor 17 formed on the insulation layer 16 b, a second spiral conductor 18 formed on the insulation layer 16 c, a first lead conductor 19 formed on the insulation layer 16 a, and a second lead conductor 20 formed on the insulation layer 16 d.

The insulation layers 16 a to 16 e insulate between conductor patterns, or conductor patterns and the magnetic layer 16 f, and function to secure the flatness of a base surface on which the conductor patterns are formed. For materials of the insulation layers 16 a to 16 e, it is preferable to use a resin excellent in electric and magnetic insulation and having a good workability. Preferably, a polyimide resin and an epoxy resin are used. Preferably, Cu, Al and the like excellent in conductivity and workability are used for conductor patterns. The conductor patterns can be formed by an etching method and an additive method (plating) using photolithography.

An opening 25 piercing through the insulation layers 16 b to 16 e is provided at an interior portion of the first and second spiral conductors 17 and 18 as center regions of the insulation layers 16 b to 16 e. A magnetic substance 26 to form a closed path is filled into between the first magnetic substrate 11 a and the second magnetic substrate 11 b, within the opening 25. A composite ferrite and the like are preferably used for the magnetic substance 26.

The magnetic layer 16 f is formed on a surface of the insulation layer 16 e. The magnetic substance 26 within the opening 25 is formed by curing a paste of composite ferrite (a resin containing a magnetic powder). At a curing time, the resin is contracted, and unevenness occurs at an opening portion. To decrease this unevenness, it is preferable to coat the paste on a whole surface of the insulation layer 16 e as well as the interior portion of the opening 25. The magnetic layer 16 f is formed to secure this flatness.

The adhesive layer 16 g is a layer necessary to bond the magnetic substrate 11 b onto the magnetic layer 16 f. The adhesive layer 16 g also functions to suppress the unevenness of the surfaces of the magnetic substrate 11 b and the magnetic layer 16 f, and increasing close adhesiveness. While not particularly limited, an epoxy resin, a polyimide resin, and a polyamide resin can be used as materials of the adhesive layer 16 g.

The first spiral conductor 17 corresponds to the inductor element 14 a shown in FIG. 2. An internal peripheral end of the first spiral conductor 17 is connected to the first terminal electrode 13 a via a first contact hole conductor 21 and the first lead conductor 19 piercing through the insulation layer 16 b. An external peripheral end of the first spiral conductor 17 is connected to the third terminal electrode 13 c via a third lead conductor 23.

The second spiral conductor 18 corresponds to the inductor element 14 b shown in FIG. 2. An internal peripheral end of the second spiral conductor 18 is connected to the second terminal electrode 13 b via a second contact-hole conductor 22 and the second lead conductor 20 piercing through the insulation layer 16 d. An external peripheral end of the second spiral conductor 18 is connected to the fourth terminal electrode 13 d via a fourth lead conductor 24.

The first and second spiral conductors 17 and 18 have the same plane surface shape, and are provided at the same position as a planar view. The first and second spiral conductors 17 and 18 are completely overlapped with each other, and therefore, a strong magnetic coupling occurs between the first and second spiral conductors 17 and 18. Based on the above configuration, conductor patterns within the common-mode filter layer 12 a constitute a common mode filter.

To normally operate the common mode filter in a desired transmission frequency, a cutoff frequency fc (MHz) of differential mode noise needs to be set to about three to five times of the desired transmission frequency. For example, to normally operate the common mode filter when a transmission frequency is 800 MHz, the cutoff frequency fc (MHz) needs to be set to about 2.4 GHz to 4 GHz. For the common-mode filter elements to satisfy the condition described above, a width W and a length L of the first and second spiral conductors 17 and 18 need to satisfy the relational equation (1).

√(L/W)<(7.6651−fc)/0.1385  (1)

The length L of the spiral conductors is a total length from the inside of a spiral to an external end of the spiral.

Meanwhile, DC resistance of the common mode filer is set equal to or higher than 0.5Ω and equal to or lower than 5Ω. This is because when the DC resistance of the common mode filer is equal to or higher than 0.5Ω, a protection voltage equal to or higher than 5 kV can be obtained in the IC at a latter stage. A conventional circuit configured by combining a varistor of 6 pF that is a general ESD protection element and a common mode filter is known to be able to secure a protection voltage of 5 kV. The present invention can also provide an ESD protection function capable of obtaining a protection voltage equivalent to this, and having a smaller electrostatic capacitance than that of a varistor and having an excellent discharge characteristic. The reason for setting the DC resistance equal to or lower than 5Ω is to prevent reduction of the cutoff frequency fc of differential mode noise.

It is particularly preferable that DC resistance of the common mode filter is equal to or higher than 1Ω and equal to or lower than 3Ω. This is because when the DC resistance is equal to or higher than 1Ω, a protection voltage equal to or higher than 7 kV can be obtained in the IC at a latter stage, and because a protection voltage exceeding that of the conventional circuit configured by combining a varistor of 6 pF and a common mode filter can be obtained. The reason for setting the DC resistance equal to or lower than 3Ω is to securely prevent reduction of the cutoff frequency fc of the differential mode noise described above.

To set the DC resistance of the common mode filter to equal to or higher than 0.5Ω, it suffices that a conductor width of the first and second spiral conductors 17 and 18 within the common-mode filter layer 12 a is set small, a conductor width is set small, and the number of turns of the spirals is increased. However, it is not preferable to decrease the conductor width of the first and second spiral conductors 17 and 18 or to increase the number of turns of the spirals. This is because the shape of the spiral conductor does not satisfy the above relational equation of a cutoff frequency. Therefore, to set the DC resistance to equal to or higher than 0.5Ω while satisfying the above relational equation, it is effective to decrease the thickness of the spiral conductors 17 and 18. It is preferable that the thickness of the first and second spiral conductors 17 and 18 is equal to or smaller than 10 μm. When the thickness of the spiral conductors is equal to or smaller than 10 μm, the above relational equation can be satisfied in the transmission frequency of 800 MHz.

The ESD protection element layer 12 b includes a base insulation layer 27, first and second gap electrodes 28 and 29 formed on a surface of the base insulation layer 27, and a ESD absorbing layer 30 covering the first and second gap electrodes 28 and 29. A layer structure near the first gap electrode 28 is a portion functioning as the first ESD protection element 15 a shown in FIG. 2, and a layer structure near the second gap electrode 29 is a portion functioning as the second ESD protection element 15 b. One end of the first gap electrode 28 is connected to the first terminal electrode 13 a, and the other end of the first gap electrode 28 is connected to the fifth terminal electrode 13 e. One end of the second gap electrode 29 is connected to the second terminal electrode 13 b, and the other end of the second gap electrode 29 is connected to the sixth terminal electrode 13 f.

FIG. 4 is a schematic plan view showing a positional relationship between the gap electrodes 28 and 29 and other conductor patterns.

As shown in FIG. 4, gaps 28G and 29G held by the gap electrodes 28 and 29 are provided at positions not overlapped on the plane with the first and second spiral conductors 17 and 18 and the first and second lead conductors 19 and 20 constituting the common mode filter. Although not particularly limited, in the first embodiment, the gaps 28G and 29G are provided in an open region between the spiral conductors 17 and 18 and the opening 25 at the inside of the spiral conductors 17 and 18. While details thereof are described later, because ESD protection elements are partially damaged or deformed due to absorption of ESD, conductor patterns have a risk of being damaged at the same time when the conductor patterns are arranged at a position overlapped with the ESD protection elements. However, because the gaps 28G and 29G of the ESD protection elements are provided at positions deviated from the conductive patterns, influence to upper and lower layers can be suppressed when the ESD protection elements are partially destroyed by ESD, and a composite electronic device having higher reliability can be realized.

FIGS. 5A and 5B are examples of a layer structure near the first gap electrode 28 in the ESD protection layer 12 b, where FIG. 5A is a schematic plan view and FIG. 5B is a schematic cross-sectional view. A configuration of the second gap electrode 29 is the same as that of the first gap electrode 28, and therefore redundant explanations will be omitted.

The ESD protection layer 12 b includes the base insulation layer 27 formed on a surface of the magnetic substrate 11 a, a pair of the electrodes 28 a and 28 b constituting the first gap electrode 28, and the ESD absorbing layer 30 arranged between the electrodes 28 a and 28 b. In this ESD protection layer 12 b, the ESD absorbing layer 30 functions as a low-voltage discharge type ESD protection material. The ESD absorbing layer 30 is designed to secure initial discharge between the electrodes 28 a and 28 b via the ESD absorbing layer 30 when an overvoltage of ESD is applied.

The base insulation layer 27 is made of an insulation material. In the first embodiment, the base insulation layer 27 covers a whole surface of the magnetic substrate 11 a from easiness of manufacturing. However, the base insulation layer 27 does not need to cover the whole surface when the base insulation layer 27 is at least a base of the electrodes 28 a and 28 b and the ESD absorbing layer 30.

As a detailed example of the base insulation layer 27, there can be suitably used a substance obtained by forming an insulation film made of a low-dielectric-constant material having a dielectric constant equal to or lower than 50, preferably equal to or lower than 20, of NiZn ferrite, aluminum, silica, magnesia, and aluminum nitride, on the surface of the first magnetic substrate 11 a. A method of forming the base insulation layer 27 is not particularly limited, and a known method can be applied such as a vacuum deposition method, a reactive deposition method, a sputtering method, an ion plating method, and a gas phase method such as CVD and PVD. A film thickness of the base insulation layer 27 can be suitably set.

A pair of the electrodes 28 a and 28 b is arranged with a distance from each other on the surface of the base insulation layer 27. In the first embodiment, the pair of the electrodes 28 a and 28 b is arranged opposite to each other with a gap distance ΔG at a predetermined position on the base insulation layer 27.

As materials constituting the electrodes 28 a and 28 b, there can be mentioned at least one kind of metal or an alloy of metals selected from Ni, Cr, Al, Pd, Ti, Cu, Ag, Au, and Pt, for example. However, metals are not particularly limited thereto. In the first embodiment, while the electrodes 28 a and 28 b are formed in a rectangular shape as a planar view, the shape is not particularly limited thereto, and can be a comb-teeth shape or a saw-teeth shape.

The gap distance ΔG between the electrodes 28 a and 28 b can be suitably set by considering a desired discharge characteristic. Although not particularly limited, the gap distance ΔG is usually about 0.1 to 50 μm. From the viewpoint of securing low-voltage initial discharge, the gap distance ΔG is more preferably about 0.1 to 20 μm, and further preferably about 0.1 to 10 μm. A thickness of the electrodes 28 a and 28 b can be suitably set, and it is usually about 0.05 to 10 μm although not particularly limited thereto.

The ESD absorbing layer 30 is arranged between the electrodes 28 a and 28 b. In the first embodiment, the ESD absorbing layer 30 is laminated on the surface of the base insulation layer 27 and on the electrodes 28 a and 28 b. A size and a shape and a layout position of the ESD absorbing layer 30 are not particularly limited so long as the ESD absorbing layer 30 is designed to secure initial discharge between the electrodes 28 a and 28 b via the self when an overvoltage is applied.

The ESD absorbing layer 30 is a composite of a sea-island structure having an aggregate of a conductive inorganic material 33 dispersed discontinuously in a matrix of an insulation inorganic material 32. In the first embodiment, the ESD absorbing layer 30 is formed by sequentially performing sputtering. Specifically, the conductive inorganic material 33 is partially (incompletely) filmed by sputtering, on at least one of an insulation surface of the base insulation layer 27 and the electrodes 28 a and 28 b. Thereafter, the insulation inorganic material 32 is sputtered, thereby forming a composite of a laminating structure of a layer of the conductive inorganic material 33 dispersed in a so-called island shape and a layer of the insulation inorganic material 32 covering the layer of the conductive inorganic material 33.

As an example of the insulation inorganic material 32 constituting a matrix, a metal oxide and a metal nitride can be mentioned, but the material is not limited thereto. Considering insulation and costs, Al₂O₃, TiO₂, SiO₂, ZnO, In₂O₃, NiO, CoO, SnO₂, V₂O₅, CuO, MgO, ZrO₂, AlN, BN, and SiC are preferable. Either one kind or two or more kinds of these materials can be used. Among these materials, from the viewpoint of giving high insulation to an insulation matrix, Al₂O₃ or SiO₂ is more preferably used. On the other hand, from the viewpoint of giving semiconductivity to the insulation matrix, TiO₂ or ZnO is more preferably used. When semiconductivity is given to the insulation matrix, ESD protection elements having excellent discharge starting voltage and clamp voltage can be obtained. While a method of giving semiconductivity to the insulation matrix is not particularly limited, TiO₂ or ZnO can be used as a single material, or these materials can be used together with other insulation inorganic material 32. Particularly, TiO₂ has oxygen easily lost at the time of sputtering in an argon atmosphere, and electric conductivity tends to become high. Therefore, it is particularly preferable to use TiO₂ to give semiconductivity to the insulation matrix. The insulation inorganic material 32 also functions as a protection layer that protects the pair of the electrodes 28 a and 28 b and the conductive inorganic material 33 from an optional layer (for example, the insulation layer 16 a) positioned on an upper layer.

As an example of the conductive inorganic material 33, a metal, an alloy, a metal oxide, a metal nitride, a metal carbide, and a metal boride can be mentioned. However, the conductive inorganic material 33 is not limited to these materials. Considering conductivity, C, Ni, Cu, Au, Ti, Cr, Ag, Pd, and Pt, or an alloy of these materials are preferable.

A combination of Cu, SiO₂, and Au is particularly preferable for a combination of the electrode 28, the insulation inorganic material 32, and the conductive inorganic material 33 configuring the ESD absorbing layer 30. ESD protection elements constituted by these materials are not only excellent in an electric characteristic but also are extremely advantageous in workability and costs. Particularly, a composite of a sea-island structure having an aggregate of the conductive inorganic material 33 of an island shape dispersed discontinuously can be formed in high precision and easily.

A total thickness of the ESD absorbing layer 30 is not particularly limited and can be suitably set. From the viewpoint of achieving a thinner film, the total thickness is preferably 10 nm to 10 μm. More preferably, the total thickness is 15 nm to 1 μm, and further preferably, it is 15 to 500 nm. In forming a layer of the conductive inorganic material 33 of an island shape dispersed discontinuously and a layer of the matrix of the insulation inorganic material 32 like in the first embodiment, a thickness of the layer of the conductive inorganic material 33 is preferably 1 to 10 nm, and the thickness of the layer of the insulation inorganic material 32 is preferably 10 nm to 10 μm, more preferably 10 nm to 1 μm , and further preferably 10 to 500 nm.

A method of forming the ESD absorbing layer 30 is not limited to the sputtering method described above. The ESD absorbing layer 30 can be formed by giving the insulation inorganic material 32 and the conductive inorganic material 33 onto at least one of the insulation surface of the base insulation layer 27 and the electrodes 28 a and 28 b, by applying a known thin-film forming method.

In the ESD protection layer 12 b of the first embodiment, the ESD absorbing layer 30 containing the island-shape conductive inorganic material 33 dispersed discontinuously in the matrix of the insulation inorganic material 32 functions as a low-voltage discharge type ESD protection material. By employing this configuration, it is possible to realize high-performance ESD protection elements having a small electrostatic capacitance, a low discharge starting voltage, and excellent discharge resistance. For the ESD absorbing layer 30 functioning as a low-voltage discharge type ESD protection material, a composite constituted by at least the insulation inorganic material 32 and the conductive inorganic material 33 is employed. Therefore, heat resistance is increased as compared with that of the conventional organic-inorganic composite film described above, and a characteristic does not easily vary due to external environments such as temperature and humidity. As a result, reliability is increased. The ESD absorbing layer can be formed by a sputtering method. Accordingly, productivity and economics are more increased. The ESD protection elements in the first embodiment can be configured such that the ESD absorbing layer 30 contains an element configuring the electrodes 28 a and 28 b by partially dispersing the electrodes 28 a and 28 b in the ESD absorbing layer 30 by applying a voltage to between the electrodes 28 a and 28 b.

FIG. 6 is a schematic view for explaining a principle of the ESD protection elements.

As shown in FIG. 6, when a discharge voltage based on ESD is applied to between a pair of the electrodes 28 a and 28 b, the discharge current flows from the electrode 28 a toward the electrode 28 b (ground) passing through an optional route constituted by the island-shape conductive inorganic material 33 discontinuously dispersed in the matrix of the insulation inorganic material 32 as shown by arrowheads. In this case, the conductive inorganic material 33 at a ground point having a large concentration of energy in the current route is destroyed together with the insulation inorganic material 32, and discharge energy of ESD is absorbed. Although a destroyed route becomes nonconductive, ESD can be absorbed at plural times because many current routes are formed by the island-shape conductive inorganic material 33 discontinuously dispersed, as shown in FIG. 6.

As explained above, the composite electronic device 100 according to the first embodiment includes low-voltage type ESD protection elements having a small electrostatic capacitance, a low discharge starting voltage, and excellent discharge resistance, heat resistance, and weatherability. Therefore, a composite electronic device functioning as a common mode filter including a high-performance ESD protection function can be realized.

According to the first embodiment, the insulation inorganic material 32 and the conductive inorganic material 33 are used as materials of the ESD protection layer 12 b. Because a resin is not contained in various materials configuring the ESD protection layer 12 b, the ESD protection layer 12 b can be formed on the magnetic substrate 11 a, and the common-mode filter layer 12 a can be formed on the ESD protection layer 12 b. To form the common-mode filter layer 12 a by a so-called thin-film forming method, a heat processing step at 350° C. or above is necessary. To form the common-mode filter layer 12 a by a so-called layer laminating method of sequentially laminating ceramic sheets formed with conductor patterns, a heat processing step at 800° C. is necessary. However, when the insulation inorganic material 32 and the conductive inorganic material 33 are used as materials of the ESD protection layer, the materials can bear the heat processing step, and ESD protection elements functioning normally can be formed. The ESD protection elements can be formed on a sufficiently flat surface on a magnetic substrate, and a fine gap of gap electrodes can be stably formed.

According to the first embodiment, formation positions of the gap electrodes are not overlapped on a plane surface with the first and second spiral conductors configuring the common mode filter, and the gap electrodes are provided at positions deviating from the conductor patterns. Therefore, influence to upper and lower directions can be suppressed when the ESD protection elements are partially destroyed by ESD, and a composite electronic device having higher reliability can be realized.

According to the first embodiment, as shown in FIG. 2, the composite electronic device 100 is mounted on the pair of signal lines, and the ESD protection elements 15 a and 15 b are provided nearer to the input side of the signal lines than to the common mode filter 14 a. Therefore, absorption efficiency of an overvoltage of the ESD protection elements can be increased. Usually, an overvoltage of ESD is an abnormal voltage having no balance in impedance matching, and therefore, is once reflected at an input end of the common mode filter. This reflection signal is superimposed with an original signal waveform. A signal of an increased voltage is absorbed at once by the ESD protection elements. That is, a common mode filter at a latter stage of the ESD protection elements increases a size of the waveform to larger than that of the original waveform. Therefore, it is possible to generate a state that the signal can be more easily absorbed by the ESD protection elements than when the signal is absorbed in a state of a low voltage level. By inputting a once-absorbed signal into the common mode filter in this way, fine noise can be removed.

Furthermore, according to the present embodiment, DC resistance of the common-mode filter elements is set equal to or higher than 0.5Ω. Therefore, a high-performance ESD protection function having a protection voltage equal to or higher than 5 kV for the IC connected to the latter stage can be provided.

A method of manufacturing the composite electronic device 100 according to the first embodiment is explained in detail next.

FIG. 7 is a flowchart showing a manufacturing step of the composite electronic device.

In the method of manufacturing the composite electronic device 100, the first magnetic substrate 11 a is first prepared (Step S101), the ESD protection layer 12 b is formed on the surface of the first magnetic substrate 11 a (Steps S102 to S104), and the common-mode filter layer 12 a is formed on the surface of the ESD protection layer 12 b (Steps S105 to S111). The second magnetic substrate 11 b is laminated (Step S112). Thereafter, the terminal electrodes 13 a to 13 f are formed on the external peripheral surface (Step S113), thereby completing the composite electronic device 100 having the common-mode filter layer 12 a and the ESD protection layer 12 b sandwiched between the first and second magnetic substrates 11 a and 11 b.

The method of manufacturing the composite electronic device 100 according to the first embodiment is used to consistently form the common-mode filter layer 12 a and the ESD protection layer 12 b by the thin-film forming method. The thin-film forming method is a method of forming a multi-layer film having insulation layers and conductor layers alternately formed, by forming insulation layers by coating a photosensitive resin, exposing and developing this layer, and thereafter by repeating a step of forming conductor patterns on a surface of the insulation layers. A step of forming the ESD protection layer 12 b and the common-mode filter layer 12 a is explained in detail below.

In the formation of the ESD protection layer 12 b, the base insulation layer 27 is first formed on the surface of the magnetic substrate 11 a (Step S102). A method of forming the base insulation layer 27 is not particularly limited, and a known method can be applied such as a vacuum deposition method, a reactive deposition method, a sputtering method, an ion plating method, and a gas phase method such as CVD and PVD. A film thickness of the base insulation layer 27 can be suitably set.

The gap electrodes 28 and 29 are formed on the surface of the base insulation layer 27 (Step S103). The gap electrodes 28 and 29 can be formed by forming a film of an electrode material on the whole surface of the base insulation layer 27, and thereafter by patterning the electrode material. Because the gap distance ΔG between the pair of electrodes is very fine like about 0.1 to 50 μm, a high-precision patterning is required, and flatness of the base surface is also required. The base insulation layer 27 is formed on the magnetic substrate 11 a having high flatness. Because the base insulation layer 27 has high flatness, a fine gap width can be controlled in high precision.

The ESD absorbing layer 30 is formed on the surface of the base insulation layer 27 on which the gap electrodes 28 and 29 are formed (Step S104). Specifically, the conductive inorganic material 33 is partially (incompletely) filmed by sputtering, on at least one of the insulation surface of the base insulation layer 27 and the electrodes 28 a and 28 b. Thereafter, the insulation inorganic material 32 is sputtered, thereby forming a composite of a laminating structure of a layer of the conductive inorganic material 33 dispersed in an island shape and a layer of the insulation inorganic material 32 covering the layer of the conductive inorganic material 33. As a result, the ESD protection layer 12 b is completed.

In the formation of the common-mode filter layer 12 a, insulation layers and conductor patterns are alternately formed, thereby forming the insulation layers 16 a to 16 e, the first and second spiral conductors 17 and 18, and the first and second lead conductors 19 and 20 (Steps S105 to S109). Specifically, after the insulation layer 16 a is formed on the ESD protection layer 12 b, the first lead conductor 19 is formed on the insulation layer 16 a (Step S105). Next, after the insulation layer 16 b is formed on the insulation layer 16 a, the first spiral conductor 17 is formed on the insulation layer 16 b, and a contact hole 21 piercing through the insulation layer 16 b is formed (Step S106). After the insulation layer 16 c is formed on the insulation layer 16 b, the second spiral conductor 18 is formed on the insulation layer 16 c (Step S107). Next, after the insulation layer 16 d is formed on the insulation layer 16 c, the second lead conductor 20 is formed on the insulation layer 16 d, and the contact hole 22 piercing through the insulation layer 16 d is formed (Step S108). Further, the insulation layer 16 e is formed on the insulation layer 16 d (Step S109).

The insulation layers 16 a to 16 e can be formed by spin coating a photosensitive resin on the base surface, and by exposing and developing the photosensitive resin. Particularly, the insulation layers 16 b to 16 e can be formed as insulation layers having the opening 25. Conductor patterns such as spiral conductors can be formed by forming a conductor layer by a deposition method or by a sputtering method, and thereafter by patterning the conductor layer. The conductive layer at this time needs to have a thickness set in advance to satisfy the above relational equation. The spiral conductor formed by patterning the conductive layer also needs to have a width set in advance to satisfy the above relational equation (1).

The magnetic substance 26 is filled into the opening 25, and the magnetic layer 16 f is formed on the surface of the insulation layer 16 e as well (Step S110). Thereafter, the adhesive layer 16 g is formed (Step S111), and the second magnetic substrate 11 b is bonded via the adhesive layer 16 g (Step S112). The terminal electrodes 13 a to 13 f are formed on an external peripheral surface of a laminated body (Step S113), thereby completing the composite electronic device 100.

As explained above, the method of manufacturing a composite electronic device according to the first embodiment is a thin-film forming method for consistently forming the ESD protection layer 12 b and the common-mode filter layer 12 a. Therefore, the composite electronic device can be manufactured without via a special manufacturing step. The method of manufacturing a composite electronic device according to the first embodiment is for forming the ESD protection layer 12 b on the magnetic substrate 11 a, and forming the common-mode filter layer 12 a on the ESD protection layer 12 b. Therefore, the ESD protection elements can be formed on the surface of the magnetic substrate 11 a having a relatively flat surface, and a composite electronic device having combined high-quality ESD protection elements and a common-mode filter can be manufactured.

FIG. 8 is a schematic exploded perspective view showing a configuration of a composite electronic device according to a second embodiment of the present invention.

As shown in FIG. 8, a composite electronic device 200 according to this embodiment is characterized in that the shape of the first and second spiral conductors 17 and 18 is not a rectangular spiral pattern, but a curved spiral pattern (a circular spiral pattern). The spiral conductors 17 and 18 do not need to have a curve in its entirety, and is sufficient to have only partly a curved shape such as a corner portion in a curved shape. When the first and second spiral conductors 17 and 18 have a circular spiral shape, the total length of the spiral conductors can be shorter than that when these spiral conductors have a rectangular spiral shape. Accordingly, a cutoff frequency of differential mode noise of the common mode filter can be set higher. On the other hand, when the total length of the spiral conductors 17 and 18 becomes short, DC resistance decreases. Therefore, in the case of the circular spiral shape, a thickness of the conductors needs to be smaller. Other configurations of the composite electronic device 200 are identical to those of the composite electronic device 100 according to the first embodiment. Therefore, elements having the same configurations are denoted by like reference numerals, and detailed explanations thereof will be omitted.

As explained above, according to the second embodiment, because the first and second spiral conductors 17 and 18 have a circular spiral shape, a cutoff frequency of differential mode noise of the common mode filter can be set higher, thereby achieving a composite electronic device having higher performance. In the case of a circular spiral shape, gap electrodes can be easily formed in an open space not formed with its pattern.

A high-speed digital transmission circuit according to a preferred embodiment is explained next.

FIGS. 9A and 9B are schematic block diagrams showing a configuration of a high-speed digital transmission circuit according to a preferred embodiment of the present invention.

A high-speed digital transmission circuit 300 shown in FIG. 9A uses the composite electronic device 100 according to the first embodiment, and includes a pair of signal lines 7 a and 7 b formed on a printed substrate, a connector 7 c connected to one ends of the pair of signal lines 7 a and 7 b, an IC 6 connected to the other ends of the pair of signal lines 7 a and 7 b, and the composite electronic device 100 provided between the connector 7 c and the IC 6 on the pair of signal lines. Needless to mention, the composite electronic device 200 according to the second embodiment can be used instead of the composite electronic device 100.

The first and second terminal electrodes 13 a and 13 b of the composite electronic device 100 are connected to signal lines at the connector 7 c side, and the third and fourth terminal electrodes 13 c and 13 d are connected to signal lines at the IC 6 side. The fifth and sixth terminal electrodes 13 e and 13 f are connected to a ground line. It is preferable that the composite electronic device 100 is directly connected to the connector 7 c via only the signal lines 7 a and 7 b, and also directly connected to the IC 6.

As explained above, in the high-speed digital transmission circuit 300, an electrostatic capacitance of the ESD protection element layer 12 b included in the composite electronic device 100 is equal to or lower than 0.35 pF, and DC resistance of the common-mode filter layer 12 a is equal to or higher than 0.5Ω. Therefore, the high-speed digital transmission circuit 300 can secure a protection voltage equal to or higher than 5 kV for the IC 6 at the latter stage. Further, the high-speed digital transmission circuit 300 can provide a ESD protection function having a smaller electrostatic capacitance than that of a varistor, an excellent discharge characteristic, and increased heat resistance and weatherability.

In the high-speed digital transmission circuit 300 according to the present embodiment, because the ESD protection element layer 12 b is provided at an input side (connector 7 c side) of the common-mode filter layer 12 a, absorption efficiency of an overvoltage by the ESD protection elements can be improved. Static electricity entering from the connector 7 c is absorbed by the ESD protection element layer 12 b, but is not completely absorbed, and a part of the static electricity flows to the IC 6 side. However, because the overvoltage due to electrostatic discharge is an abnormal voltage not impedance-matched, the overvoltage is reflected by an input end of the common-mode filter layer 12 a provided at the latter stage of the ESD protection element layer 12 b. This reflection signal is superimposed with the original signal waveform, and a signal of an increased voltage is absorbed at once by the ESD protection element layer 12 b. That is, the common mode filter at the latter stage of the ESD protection elements changes the waveform to a larger waveform than the original waveform. Consequently, the ESD protection elements generate a state of more easily absorbing the signal than absorbing the signal at a low voltage level. In this way, by inputting the once-absorbed signal to the common mode filter, fine noise can be removed.

On the other hand, a high-speed digital transmission circuit 400 shown in FIG. 9B does not use the composite electronic device 100 according to the first embodiment, but is configured by using a common mode filter and ESD protection elements made of separate chip parts. That is, the high-speed digital transmission circuit 400 includes the pair of signal lines 7 a and 7 b formed on a printed substrate, the connector 7 c connected to one ends of the pair of signal lines 7 a and 7 b, the IC 6 connected to the other ends of the pair of signal lines 7 a and 7 b, a common mode filter 40 provided between the connector 7 c and the IC 6 on the pair of signal lines 7 a and 7 b, and ESD protection elements 41 a and 41 b provided at a pre-stage of the common mode filter 40.

The common mode filter 40 is the common-mode filter layer 12 a of the composite electronic device 100 in the first embodiment configured as an independent chip part. DC resistance of the common mode filter 40 is equal to or higher than 0.5Ω and equal to or lower than 5Ω, and is more preferably equal to or higher than 1Ω and equal to or lower than 3Ω. The ESD protection elements 41 a and 41 b are the ESD protection element layer 12 b of the composite electronic device 100 according to the first embodiment configured as an independent chip part. An electrostatic capacitance of the ESD protection elements 41 a and 41 b is equal to or lower than 0.35 pF. Configurations of the common mode filter 40 and the ESD protection elements 41 a and 41 b are as explained above with reference to FIGS. 3 to 5, and thus detailed explanations thereof will be omitted.

As explained above, in the high-speed digital transmission circuit 400, the electrostatic capacitance of the ESD protection elements 41 a and 41 b is also equal to or lower than 0.35 pF, and DC resistance of the common mode filter 40 is also equal to or higher than 0.5Ω. Therefore, the high-speed digital transmission circuit 400 can secure a protection voltage equal to or higher than 5 kV for the IC 6 at the latter stage. Further, the high-speed digital transmission circuit 400 can provide an ESD protection function having a smaller electrostatic capacitance than that of a varistor, an excellent discharge characteristic, and increased heat resistance and weatherability.

Furthermore, in the high-speed digital transmission circuit 400 according to the present embodiment, because the ESD protection elements 41 a and 41 b are provided at an input side (connector 7 c side) of the common mode filter 40, absorption efficiency of an overvoltage by the ESD protection elements can be increased. Static electricity entering from the connector 7 c is absorbed by the ESD protection elements 41 a and 41 b, but is not completely absorbed, and a part of the static electricity flows to the IC 6 side. However, because the overvoltage due to electrostatic discharge is an abnormal voltage not impedance-matched, the overvoltage is reflected by an input end of the common mode filter 40 provided at the latter stage of the ESD protection elements 41 a and 41 b. This reflection signal is superimposed with the original signal waveform, and a signal of an increased voltage is absorbed at once by the ESD protection element layer 12 b. That is, the common mode filter at the latter stage of the ESD protection elements changes the waveform to a larger waveform than the original waveform. Consequently, the ESD protection elements generate a state of more easily absorbing the signal than absorbing the signal at a low voltage level. In this way, by inputting the once-absorbed signal to the common mode filter, fine noise can be removed.

While preferred embodiments of the present invention have been explained above, the present invention is not limited thereto. Various modifications can be made to the embodiments without departing from the scope of the present invention and it is needless to say that such modifications are also embraced within the scope of the invention.

For example, in the first and second embodiments, although the ESD protection element layer 12 b is a lower layer and the common-mode filter layer 12 a is an upper layer, the ESD protection element layer 12 b can be an upper layer and the common-mode filter layer 12 a can be a lower layer. In this case, because the ESD protection element layer 12 b is formed on an upper surface of the common-mode filter layer 12 a, the upper surface of the common-mode filter layer 12 a needs to have a sufficient flatness.

EXAMPLES

There were prepared a sample A1 of a high-speed digital transmission circuit configured by using a composite electronic device having DC resistance of 0.5Ω in a common mode filter, and a sample A2 of a high-speed digital transmission circuit configured by using a composite electronic device having DC resistance of 1.1Ω in a common mode filter. The configuration of the high-speed digital transmission circuit is as shown in FIG. 9A. A breaking state of an IC was confirmed by applying a predetermined pulse voltage from a connector. As a result, in the sample A1, the IC was broken when a pulse voltage was about 5 kV, and a protection voltage of the IC at this time was about 5 kV. In the sample A2, the IC was broken when a pulse voltage was about 7 kV, and a protection voltage of the IC at this time was about 7 kV.

On the other hand, there were prepared a comparative sample B1 of a high-speed digital transmission circuit configured by combining a varistor having an electrostatic capacitance of 3 pF and a common mode filter, and a comparative sample B2 of a high-speed digital transmission circuit configured by combining a varistor having an electrostatic capacitance of 6 pF and a common mode filter. A breaking state of an IC was confirmed by applying a predetermined pulse voltage from a connector. As a result, in the comparative sample B1, a protection voltage of the IC was about 3 kV. In the comparative sample B2, a protection voltage of the IC was about 5 kV.

FIG. 10 is a graph showing a protection voltage of each of the above examples and corresponding comparative examples.

As shown in FIG. 10, it is clear that a protection voltage of the composite electronic device (the Sample A1) using a common mode filter having DC resistance of 0.5Ω is equivalent to a protection voltage of the combination (the comparative sample B2) of a varistor having 6 pF and a common mode filter. A protection voltage of the composite electronic device (the Sample A2) using a common mode filter having DC resistance 1.1Ω exceeds a protection voltage of the comparative sample B2. 

1. A composite electronic device comprising: ESD protection elements absorbing electrostatic discharge; and a common-mode filter element connected to the ESD protection elements, wherein an electrostatic capacitance of the ESD protection elements is equal to or lower than 0.35 pF, and DC resistance of the common-mode filter element is equal to or higher than 0.5Ω.
 2. The composite electronic device as claimed in claim 1, wherein the common-mode filter element includes first and second spiral conductors that are magnetically coupled to each other and arranged in superimposition in a laminating direction, the thickness of each of the first and second spiral conductors is equal to or smaller than 10 μm, and a width W and a length L of the first and second spiral conductors and a cutoff frequency fc (MHz) of differential mode noise satisfy a relational equation expressed by √(L/W)<(7.6651−fc)/0.1385.
 3. The composite electronic device as claimed in claim 2, wherein the first and second spiral conductors have a curved line shape.
 4. The composite electronic device as claimed in claim 2, wherein the ESD protection elements include first and second ESD protection elements, one end of the first spiral conductor is connected to the first ESD protection element, and one end of the second spiral conductor is connected to the second ESD protection element.
 5. The composite electronic device as claimed in claim 1, wherein the ESD protection elements include a base insulation layer, electrodes mutually oppositely arranged via gaps on the base insulation layer, and a static-electricity absorbing layer arranged at least between the electrodes, and the static-electricity absorbing layer is a composite having a conductive inorganic material discontinuously dispersed in a matrix of an insulation inorganic material.
 6. The composite electronic device as claimed in claim 5, wherein the insulation inorganic material is at least one kind selected from a group of Al₂O₃, TiO₂, SiO₂, ZnO, In₂O₃, NiO, CoO, SnO₂, V₂O₅, CuO, MgO, ZrO₂, AlN, BN, and SiC.
 7. The composite electronic device as claimed in claim 5, wherein the conductive inorganic material is at least one kind of metal or a metal compound of these metals selected from a group of C, Ni, Cu, Au, Ti, Cr, Ag, Pd, and Pt.
 8. The composite electronic device as claimed in claim 1, further comprising: first and second magnetic substrates; and a functional layer sandwiched between the first magnetic substrate and the second magnetic substrate, wherein the functional layer includes the ESD protection element and the common-mode filter element.
 9. A digital transmission circuit comprising: a pair of signal lines; a semiconductor IC chip connected to the pair of signal lines; ESD protection elements provided at a pre-stage of the semiconductor IC chip on the pair of signal lines; and a common mode filter provided between the ESD protection elements and the semiconductor IC chip on the pair of signal lines, wherein an electrostatic capacitance of each of the ESD protection elements is equal to or lower than 0.35 pF, and DC resistance of the common mode filter is equal to or higher than 0.5Ω. 